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stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 features ........................................................................................................................... 3 ? general description ....................................................................................................... 4 ? order information: .......................................................................................................... 4 ? pin definition ............................................................................................................ 5 ? pin configuration ...................................................................................................... 6 ? special function register ............................................................................................. 8 ? address map ............................................................................................................. 8 ? bits description ........................................................................................................ 9 ? memory .......................................................................................................................... 10 ? organization ............................................................................................................ 10 ? ram ....................................................................................................................... 10 ? embedded flash ...................................................................................................... 10 ? idle mode ..................................................................................................... 11 ? slow down mode ........................................................................................... 11 ? power-down mode .................................................................................. 12 ? device resets .......................................................................................................... 14 ? reset from reset pin ................................................................................... 14 ? watch-dog-timer ........................................................................................... 14 ? software reset ............................................................................................. 14 ? boot entrance .................................................................................................. 14 ? i/o port configuration ............................................................................................ 16 ? timer/counter ......................................................................................................... 19 ? interrupt ................................................................................................................... 2 4 ? watch dog timer .................................................................................................... 27 ? universal asynchronous serial port (uart) ......................................................... 29 ? in system programming and in application programming .................................... 34 ? in system programming (isp) ................................................................................ 34 ? in-application program (iap) ................................................................................ 37 ? other auxiliary sfrs .............................................................................................. 37 ? built-in oscillator ................................................................................................... 38 ? instructions set ............................................................................................................. 39 ? absolute maximum rating (stc11fxx) .................................................................... 42 ? dc characteristics (stc11fxx) ................................................................................. 42 ? absolute maximum rating (stc11lexx) ................................................................. 43 ? www.datasheet.co.kr datasheet pdf - http://www..net/
2 stc11fxx technical summary dc characteristics (stc11lexx) .............................................................................. 43 ? package dimension ..................................................................................................... 44 ? version history .............................................................................................................. 48 ? www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 3 features z high performance enhanced 80c51 unit. z operating voltage range: 3.3v / 5.0v z operating frequency range: 35 mhz(max). z on-chip 6k(max) flash program memory with flexible isp/iap capability z on-chip 128+128 byte scratch-pad ram. z code protection for flash memory access z two 16-bit timer/counter(t0/t1) z 6 vector-address, 4 level pr iority interrupt capability z one enhanced uart with hardware address-recognition and frame-error detection function z one 15 bits watch-dog-timer with 8-bit pre-scalar (one-time-enabled) z build in internal 6mhz rc oscillator z three power management modes: idle mode, slow down mode and power-down mode power down mode can be woken-up by any exte rnal interrupt pins and any rxd interrupt pins. z maximum 16 programmable i/o ports are available z package type : pdip-16/18/20 sop-16/18/20 www.datasheet.co.kr datasheet pdf - http://www..net/
4 stc11fxx technical summary general description stc11fxx is a single-chip 8-bit micro-controller with instruction sets fully compatible with industrial-standard 80c51 series micro controller. there is very excellent mcu kernel built in this device compared to general 80c51 mcus those take twelve oscillating cycles to finish an instruction, the device could take only one oscillating cycle to finish one instruction. there is 6k(max) bytes flash memory embedded which could be used as program or data. also the in-system programming and in -application programming mechanisms are supported. the data endurance of the embedded flash gets over 20,000 times, and 21 years data retention is guaranteed. the operation frequency reaches at 35mhzs. an user can apply a crystal oscillator for the oscillating source, or alternativel y uses the built in 6mhz rc osci llator to save system cost. the uart interfaces make the device conv enient to communicate with the peripheral component, say talking to a personal computer via rs-232 port, or communicating with a serial memory. up to 16 programmable gpios are available from stc11fxx. the stc11fxx is really the most efficient mcu adapted for simple control; say electronic scales, remote controller, security encoder/decoder, video player controller, and user interface controller. order information: part number temperature range package packing operation voltage stc11fxx-pdip industrial pdip-16/18/20 tube 3.3v / 5.0v stc11fxx-sop industrial sop-16/18/20 tube 3.3v / 5.0v .x: voltage aa: rom size bbb:adc, pwm .or. none cc:active frequency .d: temperature ?i? for industria l eeee: package type ff: pin count www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 5 pin description pin definition mnemonic package type description pdip16 pdip-18 pdip-20 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6/int p1.7/txd 10 11 12 - - 13 14 15 11 12 13 - 14 15 16 17 12 13 14 15 16 17 18 19 port1 : general-purposed i/o with weak pull-up resistance inside. when 1s are written into port1, the strong output driving pmos only turn-on two period and then the weak pull-up resistance keep the port high. p3.0/rxd/int p3.1/txd p3.2/int0 p3.3/int1 p3.4/clkout0 p3.5/clkout1 p3.6/rst p3.7/rd 2 3 - 6 7 - - - 2 3 - 6 7 8 1 10 2 3 6 7 8 9 1 11 port3 : general-purposed i/o with weak pull-up resistance inside. when 1s are written into port1, the strong output driving pmos only turn-on two period and then the weak pull-up resistance keep the port high. port3 also serves the special function of stc11fxx. reset 1 1 1 reset : a high on this pin for at least two machine cycles will reset the device. xtal1 5 5 5 crystal1 : input to the inverting oscillator amplifier. xtal2 4 4 4 crystal2 : output from the inverting amplifier. vdd 16 18 20 power gnd 8 9 10 ground www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 pin configuration stc11fxx pdip/sop-16 rst/p3.6 txd/p3.1 xtal2 xtal1 /int1/p3.3 /int/clkout/t0/p3.4 gnd p1.5 p1.2 p1.1 p1.0 p3.7 p1.6/rxd/int p1.7/txd vcc 1 8 40 /int/rxd/p3.0 rst/p3.6 txd/p3.1 xtal2 xtal1 /int1/p3.3 /int/clkout0/t0/p3.4 /int/clkout1/t1/p3.5 p1.5 p1.4 p1.2 p1.1 p1.0 p1.6/rxd/int p1.7/txd vcc 1 9 40 /int/rxd/p3.0 stc11fxx pdip/sop-18 gnd p3.7 rst/p3.6 txd/p3.1 xtal2 xtal1 /int1/p3.3 /int/clkout0/t0/p3.4 /int/clkout1/t1/p3.5 p1.5 p1.4 p1.2 p1.1 p1.0 p1.6/rxd/int p1.7/txd vcc 1 10 40 /int/rxd/p3.0 stc11fxx pdip/sop-20 /int0/p3.2 p3.7 gnd p1.3 www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 block diagram alu www.datasheet.co.kr datasheet pdf - http://www..net/
8 stc11fxx technical summary special function register address map 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f 0f8h 0ffh 0f0h b 0f7h 000000 0e8h 0efh 0e0h acc 0e7h 00000000 0d8h 0dfh 0d0h psw 0d7h 00000000 0c8h 0cfh 0c0h wdt_contr iap_data iap_addrh iap_addrl iap_cmd iap_trig iap_contr 0c7h 0x000000 11111111 00000000 00000000 xxxxxx00 xxxxxxxx 0000x000 0b8h ip saden 0bfh xx000000 00000000 0b0h p3 p3m1 p3m0 0b7h 11111111 00000000 00000000 0a8h ie saddr wktcl wktch 0afh 0x000000 00000000 00000000 00000000 0a0h p2 auxr1 0a7h 11111111 xxxx0xx0 098h scon sbuf brt 09fh 00000000 xxxxxxxx 00000000 090h p1 p1m1 p1m0 p0m1 p0m0 p2m1 p2m0 clk_div 097h 11111111 00000000 00000000 00000000 00000000 00000000 00000000 xxxxx000 088h tcon tmod tl0 tl1 th0 th1 auxr wake_clk0 08fh 00000000 00000000 00000000 00000000 00000000 00000000 0000 x000 x000x000 080h p0 sp dpl dph spistat spictl spidat pcon 087h 11111111 00000111 00000000 00000000 00x xxxxx 00000100 00000000 00110000 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 9 bits description symbol description add r bit address and symbol msb lsb initial value p0 port 0 80h p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111b sp stack pointer 81h 00000111b dpl data pointer low 82h 00000000b dph data pointer high 83h 00000000b pcon power control 87h smod smod0 - pof gf1 gf0 pd idl 00010000b tcon timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000b tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00000000b tl0 timer low 0 8ah 00000000b tl1 timer low 1 8bh 00000000b th0 timer high 0 8ch 00000000b th1 timer high 1 8dh 00000000b auxr auxiliary register 8eh t0x12 t1x12 uart_ m0x6 brtr - brtr x12- s1brs 000 0x000 b wake_ clk0 8fh rxd_pin_ ie t1_pin_ ie t0_pin_ ie brtclko t1clko t0_clko x000x000b p1 port 1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111b p1m1 p1 configuration 0 91h 00000000b p1m0 p1 configuration 1 92h 00000000b p0m1 p0 configuration 0 93h - - - - 00000000b p0m0 p0 configuration 1 94h - - - - 00000000b p2m1 p2 configuration 0 95h 00000000b p2m0 p2 configuration 1 96h 00000000b clk_div clock dvder 97h clks2 clks1 clks0 xxxxx000b scon serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00000000b sbuf serial buffer 99h xxxxxxxxb brt dedicate baud-rate time 9ch 00000000b p2 port 2 a0h 11111111b auxr1 a2h uart_p1 gf2 dps 0xxx0xx0 ie interrupt enable a8h ea - et2 es et1 ex1 et0 ex0 0x000000b saddr slave address a9h 00000000b wktcl wake up control register low aah - - 00000000b wakch wake up control register high abh wkten 0xxx0000b p3 port 3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 11111111b p3m1 p3 configuration 0 b1h 00000000b p3m0 p3 configuration 1 b2h 00000000b ip interrupt priority low b8h - - pt2 ps pt1 px1 pt0 px0 xx000000b saden slave address mask b9h 00000000b wdt_contr watch dog timer control register c1h wdt_fl ag en_wdt clr_wd t idle_ wdt ps2 ps1 ps0 xx000000b iap_data isp/iap flash data register c2h 11111111b iap_addr h isp/iap address high c3h 00000000b iap_addrl isp/iap address low c4h 00000000b iap_cmd isp/iap command register c5h ms1 ms0 xxxxx000b iap_trig isp/iap_command trigger c6h xxxxxxxxb iap_contr isp/iap control register c7h iapen swbs swrst- cmd_fail - - wt2 wt1 wt0 0000x000b psw program status word d0h cy ac f0 rs1 rs0 ov - p 00000000b acc accumulator e0h acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000b b b register f0h 00000000b www.datasheet.co.kr datasheet pdf - http://www..net/
10 stc11fxx technical summary memory organization ram there are 256 bytes ram built in stc11fxx. t he user can visit the leading 128-byte ram via direct addressing instructions , we name those ram as direct ram that occupies address space 00h to 7fh. followed 128-byte ram can be visited via indi rect addressing instructions, we name those ram as indirect ram that occupied address space 80h to ff h. embedded flash there is totally 6k(max) byte flash embedded in the stc11fxx. the user can configure the whole flash to store his application program, or he can configure the flash for both storage of application (ap) program and in-system-program (isp) code, even he can configure the flash for storage of ap, isp, and in-application-program (iap) memory. if there is requirement from the user?s applic ation program to store nonvolatile parameters, the user can allocate part of the embedded flash as iap memory by part no.. 00-7f ram, access it via direct addressing 80-ff sfr, access it via direct addressing 80-ff indirect on-chip ram, access it via indirect addressing 00 80 ff address space for stc11fxx ram 7f www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 power saving idle mode an instruction setting sfr pcon . 0 causes the device go into the idle mode, the internal clock is gated off to the cpu but not to the interru pt, timer, wdt and serial port functions. there are two ways to termi nate the idle. activation of any enabled interrupt will cause pcon . 0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti instruction, t he next instruction to be executed will be the one following the instruction that puts the device into idle. another way to wake-up from idle is to pull pin rst high to generate internal hardware reset. slow down mode a clock divider(clkdiv) in the frond end of the device is designed to slow down the operation speed of stc11fxx, to save the operating po wer dynamically. different from the same register in stc11fxx mcu, the content in sfr clk_div is always effective without the need to operate in idle mode. sfr: clk_div bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - - - - clks2 clks1 clks0 {cks2, cks1, cks0}: clock selector under idle mode {0, 0,0} : = (default) in idle mode, clock is not divided (default state) {0, 0, 1} : = in idle mode, clock is divided by 2 {0, 1, 0} : = in idle mode, clock is divided by 4 {0, 1, 1} : = in idle mode, clock is divided by 8 {1, 0,0} : = in idle mode, clock is divided by 16 {1, 0, 1} : = in idle mode, clock is divided by 32 {1, 1, 0} : = in idle mode, clock is divided by 64 {1, 1, 1} : = in idle mode, clock is divided by 128 www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 power-down mode an instruction setting pcon . 1 causes the device go into the power-down mode. in the power-down mode, the on-chip oscillator is sto pped. the contents of on-chip ram and sfrs are maintained. in the power down mode, the on-chip oscillator is stopped. the contents of on-chip ram and sfrs are maintained. the power-down mode can be woken-up by reset pin, external interrupt int0 ~ int3 and keypad interrupt. when it is woken-up by reset, the program will execute from the address 0x0000. be carefully to keep r eset pin active for at least 10ms in order for a stable clock. if it is woken-up from i/o, the cpu will rework through jumping to related interrupt service routine. before the cpu rework, the cl ock is blocked and counted until 32768 in order for denouncing the unstable clock. to use i/o wake -up, interrupt-related registers have to be enabled and programmed accurately before entering power-down. pay attention to have at least one ?nop? instruction subsequent to the power-down instruction if i/o wake-up is used. sfr: pcon bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 smod smod0 - pof gf1 gf0 pd idl smod:= double baud rate of uart interface 0 : = (default) keep normal baud rate when the uart is used in mode 1,2 or 3. 1 : = double baud rate when the uart is used in mode 1,2 or 3. smod0:= sm0 / fe bit select for sfr scon . 7 ; setting this bit will set sfr scon . 7 as frame error function. clearing it to set scon.7 as one bit of uart mode selection bits. (this bit is serial port related, see t he further description about the serial port) pof:= power-on flag this bit will be set after the device was powered on. it must be cleared by the user?s software. gf1, gf0:= general purpose flags the user can take them as ram to hold bit variables. pd:= power-down switch www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 13 set this bit to drive the device enter power-down mode. idl:= idle flag set this bit to drive the device enter idle mode. www.datasheet.co.kr datasheet pdf - http://www..net/
14 stc11fxx technical summary device resets there are 6 sources could generate internal reset. they are power on, reset pin, power monitor unit(pmu), watch-dog-timer and user-invoked software reset. reset from reset pin the reset pin, which is the input to the schmi tt trigger, is input pin for chip reset. a level change of reset pin have to keep at least 24 c ycles plus 10us in order for cpu internal sampling use. watch-dog-timer an overflow of watch-dog-time r will generate a internal reset. software reset writing an ?1? to swrst bit in sfr iap_contr can invoke a internal reset. boot entrance the following procedure describes how doe s this device select the boot entrance. sampling (24 clocks) internal reset reset pin wdt reset software reset por enlvro opf cpf enlvrc stc11fxx interrupt circuit www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 if ( hwbs2 ==0) then swbs = 1 else swbs keeps unchanged end if ( swbs ==1) { boot from isp code else boot from ap code swbs keeps unchanged if ( swbs ==1) { boot from isp code else boot from ap code end power-up reset-pin press wdt overflow, power monitor un it reset, and software reset if ( ( hwbs ==0) or ( hwbs2 ==0) ) then swbs = 1 else swbs keeps unchanged end if ( swbs ==1) { boot from isp code else boot from ap code www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 functional description i/o port configuration there are 15(max) gpio available from this devic e. all io pins on stc11fxx may be independently configured to one of four modes: quasi-bidirect ional (standard 8051 port output), push-pull output, open-drain output or input- only. all port pins default to quasi-bidire ctional after reset. each port pin has a schmitt-triggered input for improved input noise reject ion. during power-down, all the schmitt-triggered inputs are disabled with the exception of severa l pins which may be used to wake-up the device. the use can use p3.2(int0), p3.3(int1), p3.0(int), p1 .6(int), to drive this device escape power-down mode. therefore such kind of pins shoul d not be left floating during power-down. there are several special function regist ers designed to configure those i/o ports. sfr: p1m0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 p1m07 p1m06 p1m0 5 p1m04 p1m03 p1m02 p1m01 p1m00 sfr: p1m1 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 p1m17 p1m16 p1m1 5 p1m14 p1m13 p1m12 p1m11 p1m10 sfr: p3m0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 p3m07 p3m06 p3m0 5 p3m04 p3m03 p3m02 p3m01 p3m00 sfr: p3m1 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 p3m17 p3m16 p3m1 5 p3m14 p3m13 p3m12 p3m11 p3m10 configuration of i/o port p x m0 n p x m1 n port mode 0 0 quasi-bidirectional(default) 0 1 push-pull output 1 0 input only (high-impedance) 1 1 open-drain output ( x = 1 or 3 n = 7, 6, 5, 4, 3, 2, 1 or 0 ) www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 17 quasi-bidirectional mode port pins in quasi-bidirectional output mode fu nction similar to the standard 8051 port pins. a quasi-bidirectional port can be used as an input and output without the need to reconfigure the port. this is possible because when the port outputs logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin outputs low, it is driven strongly and able to sink a large current. there are three pull-up tran sistors in the quasi-bidi rectional output that serve different purposes. one of these pull-ups, called the ?very weak? pull-up, is turned on whenever the port register for the pin contains a logic ?1?. this very weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull-up, called the ?weak? pull-up, is turned on when the port register for the pin contains a logic ?1? and the pin itself is also at a logic ?1? level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a ?1?. if this pin is pulled low by the external device, this weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage. the third pull-up is referred to as the ?strong? pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional po rt pin when the port register changes from a logic ?0? to a logic ?1?. when this occurs, the strong pull-up turns on for two cpu clocks, quickly pulling the port pin high. vdd vdd vdd port pin 2 clocks delay strong very weak weak input data port latch data www.datasheet.co.kr datasheet pdf - http://www..net/
18 stc11fxx technical summary open-drain output the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port register contains logic ?0?. to use this configuration in application, a port pin must have an external pull- up, typically tied to vdd. the input path of the port pin in this configuration is the same as quasi-bidirection mode. port pin input data port latch data input-only mode the input-only configuration is a schmitt-trigge red input without any pull-up resistors on the pin. port pin input data push-pull output the push-pull output configuration has the sa me pull-down structure as both the open-drain and the quasi-bidirectional output modes, but pr ovides a continuous strong pull-up when the port register contains a logic ?1?. the push-pu ll mode may be used when more source current is needed from a port output. vdd port pin input data port latch data www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 19 timer/counter stc11fxx has two 16-bit timers, and they are named t0 and t1 . each of them can also be used as a general event counter, which counts the transition from 1 to 0. since the stc11fxx is a risc-like mcu which execute faster than traditional 80c51 mcu from other providers. based on consideration of compatib ility with traditional 80c51 mcus, the frequency of the clock source for t0 and t1 is designed to be selectable between oscillator frequency divi ded-by-12 (default) or oscillator frequency. the user can configure t0/t1 to work under mode-0, mode-1, mode-2 and mode-3. it is fully the same to a traditional 80c51 mcu. there are two sfr designed to configure timers t0 and t1 . they are tmod , tcon . the user also should take a glace of sfr auxr which decide the frequency of the clock source driving the t0 and t1 . sfr: tmod (timer mode control register) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 gate c//t m1 m0 gate c//t m1 m0 (f or timer 1 use ) (f or timer 0 use ) gate: = gating control 0 : = (default) timer x is enabled whenever ?tr x ? control bit is set. 1 : = timer/counter x is enabled only while ?/int x ? pin is high and ? tr x ? control bit is set. c//t: = timer or counter function selector. 0 : =timer, 1 : =counter 0 : = (default) configure t x as timer use 1 : = configure t x as counter use {m1, m0}: mode select {0, 0} : = configure t x as 13-bit timer/counter {0, 1}: = configure t x as 16-bit timer/counter {1, 0} : = configure t x as 8-bit timer/counter with automatic reload capability {1, 1} : = for t0, set tl0 as 8-bit timer/counter, th0 is locked into 8-bit timer for t1, set timer/counter1 stopped www.datasheet.co.kr datasheet pdf - http://www..net/
20 stc11fxx technical summary sfr: tcon bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tf1 : = timer1 overflow flag. this bit is automatically set by hardware on t1 overflow, and will be automatically cleared by hardware when the processor vector s to the interrupt routine. tr1 : = timer1 run control bit. 0 : = (default) stop t1 counting 1 : = start t1 counting tf0 : = timer0 overflow flag. this bit is automatically set by hardware on t0 overflow, and will be automatically cleared by hardware when the processor vector s to the interrupt routine. tr0 : = timer0 run control bit. 0 : = (default) stop t0 counting 1 : = start t0 counting ie1 : = external interrupt-1 flag. this bit is automatically set by hardware on interrupt from the external interrupt-1, and will be automatically cleared by hardware when t he processor vectors to the interrupt routine. it1 : = interrupt-1 type control bit. 0 : = (default) set the interrupt-1 triggered by low duty from pin ex1 1 : = set the interrupt-1 triggered by negative falling edge from pin ex1 ie0 : = external interrupt-0 flag. this bit is automatically set by hardware on interrupt from the external interrupt-0, and will be automatically cleared by hardware when t he processor vectors to the interrupt routine. it0 : = interrupt-0 type control bit. 0 : = (default) set the interrupt-0 triggered by low duty from pin ex1 1 : = set the interrupt-0 triggered by negative falling edge from pin ex1 www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 21 sfr: auxr (auxiliary register) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t0x12 t1x12 uartm0x6 brtr brtx12 s1brs t0x12 : = t0 clock source selector 0: = (default) set the frequency of the clock source for t0 as the oscilla tor frequency divided-by-12. it will compatible to the traditional 80c51 mcu. 1 : = set the frequency of the clock source for t0 as the oscillator frequency. it will drive the t0 faster than a traditional 80c51 mcu. t1x12 : = t1 clock source selector 0: = (default) set the frequency of the clock source for t1 as the oscilla tor frequency divided-by-12. it will compatible to the traditional 80c51 mcu. 1 : = set the frequency of the clock source for t1 as the oscillator frequency. it will drive the t1 faster than a traditional 80c51 mcu. urm0x6 : = baud rate selector of uart while it is working under mode-0 0: = (default) set the baud rate of the uart functional block as oscillator frequency divided-by-12. it will compatible to the traditional 80c51 mcu. 1 : = set the baud rate of the uart functional block as oscillator frequency divided-by-2. it will transmit/receive data faster than a traditional 80c51 mcu. brtr : = setting this bit will enable the baud-rate generator of secondary uart to run 0: = (default) brtx12: set this bit to set the clock source for the uart is fosc, or clear it to set the clock source for or the uart as fosc/12. 0: = (default) s1brs : = the serial port clock source selector 0: = (default) clear the serial port clock source by t1 . 1 : = set the serial port clock source from independence baud-rate generator. www.datasheet.co.kr datasheet pdf - http://www..net/
22 stc11fxx technical summary 0 1 t0 or t1 pin (sampled) tl x [4:0] th x [7:0] tf x interrupt tr x 0 1 gate /int x c / / t osc/12 0 1 auxr. x osc tl x [7:0] th x [7:0] tf x interrupt 0 1 t0 or t1 pin (sampled) tr x 0 1 gate /int x c/ / t osc/12 0 1 auxr. x osc mode 0 the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfx . the counted input is enabled to the timer when trx = 1 and either gate=0 or intx = 1. mode 0 operation is the same for timer0 and timer1. mode 1 mode1 is the same as mode0, except that the timer register is being run with all 16 bits. mode 2 mode 2 configures the timer register as an 8-bit counter (tl x ) with automatic reload. overflow from tl x does not only set tf x , but also reloads tl x with the content of th x , which is determined by user?s program. the reload leaves th x unchanged. mode 2 operation is the same for timer0 and timer1. tlx [7:0] thx [7:0] reload tf x interrupt 0 1 t0 or t1 pin (sampled) tr x 0 1 gate /int x c/ / t osc/12 0 1 auxr. x osc www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 23 mode 3 timer1 in mode3 simply holds its count, the effect is the same as setting tr1 = 1. timer0 in mode 3 enables tl0 and th0 as two separate 8-bit counters. tl0 uses the timer0 control bits such like c/t, gate, tr0, int0 and tf0. th0 is locked into a timer function (can not be external event counter) and take over the use of tr1, tf1 from timer1. th0 now controls the timer1 interrupt. 0 1 sampled t0 pin 0 1 gate /int0 tr0 tl0 [7:0] tf0 interrupt c/ / t osc/12 0 1 osc auxr. x 0 1 th0 [7:0] tf1 interrupt tr1 osc/12 0 1 osc auxr. x www.datasheet.co.kr datasheet pdf - http://www..net/
24 stc11fxx technical summary interrupt there are 6 interrupt sources available in stc11fxx. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the sfr named ie . this register also contains a global disable bit ( ea ), which can be cleared to disable all interrupts at once. each interrupt source has two corresponding bits to represent its priority. one is located in sfr named iph and the other in ip register. higher-priority inte rrupt will be not interrupted by lower-priority interrupt request. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine which request is serviced. the following table shows the internal polling sequence in the same priority level and the interrupt vector address. source vector address priority within level external interrupt 0 03h 0 (highest) timer 0 0bh 1 external interrupt 1 13h 2 timer1 1bh 3 serial port 23h 4 low voltage interrupt 33h 6 the external interrupt /int0, /int1 can each be ei ther level-activated or transition-activated, depending on bits it0 and it1 in register tcon . the flags that actually generate these interrupts are bits ie0 and ie1 in tcon . when an external interrupt is generated, the flag that generated it is cleared by the hardware w hen the service routine is vectored to only if the interrupt was transition ?activated , otherwise the external request ing source is what controls the request flag, rather than the on-chip hardware. the timer0 and timer1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter registers in most cases. when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardwar e when the service routine is vectored to. the serial port interrupt is generated by the logi cal ?1? of ri and ti. neither of these flags is cleared by hardware when the service routine is vectored to. the service routine should poll ri and ti to determine which one to request service and it will be cleared by software. www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 how does the stc11fxx take the interrupts external interrupt pins and other interrupt s ources are sampled at rising edge of each clock cycle. the samples are polled during the next cl ock cycle. if one of the flags was in a set condition of the first cycle, the second cycle of polling cycl es will find it and the interrupt system will generate an hardware lcall to the app ropriate service routine as long as it is not blocked by any of the following conditions. block conditions if one of the following conditions happens , a coming interrupt will be blocked. ? an interrupt of equal or higher prio rity level is already in progress. ? the current cycle(polling cycle) is not the final cycle in the executi on of the instruction in progress. ? the instruction in progress is reti or any write to sfrs ie , ip , registers. ? the isp/iap activity is in progress. sfr: ie bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ea - et2 es et1 ex1 et0 ex0 ea := global interrupt-controlling register set this bit, or any interrupt will be disabled et2 := timer-2 interrupt-controlling register setting this bit can enable timer-2 interrupt es := the major uart interrupt-controlling register setting this bit can enable major uart interrupt et1 := timer-1 interrupt-controlling register setting this bit can enable timer-1 interrupt ex1 := int1 interrupt-controlling register setting this bit can enable int1 interrupt et0 := timer-0 interrupt-controlling register setting this bit can enable timer-0 interrupt ex0 : int0 interrupt-controlling register setting this bit can enable int0 interrupt www.datasheet.co.kr datasheet pdf - http://www..net/
26 stc11fxx technical summary sfr: wake_clk0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - rx_pin_ie t1_pin_ie t0_pin_ie - brtclko t1clko t0clko rx_pin_ie := wake-up from rxd pin setting this bit can enable rxd pin (p3.0 .or. p1.6) wake-up from power down mode. t1_pin_ie := wake-up from timer-1 interrupt setting this bit can enable the p3.5 pin wake-up from power down mode t0_pin_ie := wake-up from timer-0 interrupt setting this bit can enable the p3.5 pin wake-up from power down mode. brtclko := setting the bit enable baud-rate generator clock out put to p1.0 ?1?: enable. ?0?:disable(default) t1clko := setting the bit enable timer-0 clock output 1/2 time-0 overflow rate to p3.5 ??1?: enable. ?0?:disable(default) t0clko := setting the bit enable timer-1 clock output 1/2 time-1 overflow rate to p3.4 ??1?: enable. ?0?:disable(default) sfr: ip bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 px2 pt2 ps pt1 px1 pt0 px0 www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 watch dog timer the watch dog timer in stc11fxx consists of an 8-bit pre-scalar timer and a 15-bit timer. the timer is one-time enabled by setting en_w dt. clearing en_wdt can not stop wdt counting. when the wdt is enabled, software sh ould always reset the timer by writing 1 to clrw bit before the wdt overflows. if stc11fxx is out of control by any disturbance, that means the cpu can not run the software nor mally, then wdt may miss the ?writing 1 to clr_wdt? and overflow w ill come. wdt overflow reset the cpu to restart. ps2 ps1 ps0 - en_ wdt clr_ wdt idl_ wdt wdt_ flag 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 8-bit prescalar 15-bit timer idle fosc/12 wdtcr register to make good use of the watch-dog-timer, the user should take notice on sfr wdt_contr . sfr: wdt_contr (wdt control register) c1h bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 wdt_flag - en_wdt clr_wdt idl _wdt ps2 ps1 ps0 wdt_flag: = when wdt overflows, this bit is set. it can be cleared by software. en_wdt: = control bit to enable watch-dog-timer. (one-time enabled, can not be disabled) 0: = (default) disable watch dog timer 1 : = enable watch dog timer start counting clr_wdt: = set this bit to recoun t wdt. hardware will auto matically clea r this bit. www.datasheet.co.kr datasheet pdf - http://www..net/
28 stc11fxx technical summary idl_wdt: = behavior controller of the wdt while the device is put under idle 0: = (default) stop watch dog timer counting 1 : = keep watch dog timer counting (so further reset could happen) {ps2, ps1, ps0} : selector of the wdt pre-scalar output. { 0, 0, 0 } : = set the pre-scaling value 2 { 0, 0, 1 } : = set the pre-scaling value 4 { 0, 1, 0 } : = set the pre-scaling value 8 { 0, 1, 1 } : = set the pre-scaling value 16 {1 , 0, 0 } : = set the pre-scaling value 32 { 1, 0, 1 } : = set the pre-scaling value 64 { 1, 1, 0 } : = set the pre-scaling value 128 { 1, 1, 1 } : = set the pre-scaling value 256 www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 29 universal asynchronous serial port (uart) the serial port of stc11fxx is duplex. it can transmit and receive simultaneously. the receiving and transmitting of the serial port share the same sfr sbuf , but actually there are two sbuf registers implemented in the chip, one is for transmitting and the other is for receiving. the serial port can be operated in 4 different modes. mode 0 generally, this mode purely is used to ex tend the i/o features of this device. operating under this mode, the device receives t he serial data or transmits the serial data via pin rxd, while there is a clock stream sh ifted via pin txd which makes convenient for external synchronization. an 8-bit data is serially transmitted/received with lsb first. the baud rate is fixed at 1/12 the oscillator frequency. if auxr .5( uartm0x6 ) is set, the baud rate is 1/2 oscillator frequency. mode1 a 10-bits data is serially transmitted through pin txd or received through pin rxd. the frame data includes a start bit ( 0 ), 8 data bits and a stop bit ( 1 ). after finishing a receiving, the device will keep the stop bit in rb8 which from srf scon . mode 0 generally, this mode purely is used to ex tend the i/o features of this device. operating under this mode, the device receives t he serial data or transmits the serial data via pin rxd, while there is a clock stream shifted via pin txd which makes convenient for external synchronization. an 8-bit data is serially transmitted/received with lsb first. the baud rate is fixed at 1/12 t he oscillator frequency. if auxr .5 ( urm0x6 ) is set, the baud rate is 1/2 oscillator frequency. mode1 a 10-bits data is serially transmitted through pin txd or received through pin rxd. the frame data includes a start bit ( 0 ), 8 data bits and a stop bit ( 1 ). after finishing a receiving, the device will keep the stop bit in rb8 which from srf scon . mode2 baud rate ( for mode 1) = 2 smod 32 x (timer-1 overflow rate) www.datasheet.co.kr datasheet pdf - http://www..net/
30 stc11fxx technical summary baud rate ( for mode 2) = 2 smod 64 x fosc an 11-bit data is serially transmitted through txd or received through rxd . the frame data includes a start bit ( 0 ), 8 data bits, a programmable 9th bit and a stop bit (1). on transmit; the 9th data bit comes from tb8 in sfr scon . on receive; the 9th data bit goes into rb8 in scon . the baud rate is programmable, and permitted to be set either 1/32 or 1/64 the oscillator frequency. mode3 mode 3 is the same as mode 2 except the baud rate is variable. n all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1 . reception is initiated in the other modes by the incoming start bit with 1 -to- 0 transition if ren = 1 . there are several sfrs related to serial port configuration described as following. sfr: scon (serial control) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri fe: = frame error bit this bit is set by the receiver when an invalid st op bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. {sm0 , sm1}: = used to set operating mode of the serial port. {0 , 0 }: = set the serial port operate under mode 0 {0 , 1 } : = set the serial port operate under mode 1 {1 , 0 } : = set the serial port operate under mode 2 {1 , 1 } : = set the serial port operate under mode 3 sm2: = enable the automatic address recognition feature in mode 2 and 3. if sm2 = 1 , ri will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or broadcast address. in mode1, if sm2=1 then ri will not be set unless a valid stop bit was received, and the received byte is a given or broadcast address. baud rate ( for mode 3) = 2 smod 32 x (timer-1 overflow rate) www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 31 bit[ i ] of compared byte = ( saden [ i ] == 1 )? saddr [ i ] : x ri = (sm2 == 1 ) && (sbuf == compared byte ) && (rb8 == 1 ) ren: = enable the serial port reception. 0: = (default) disable the serial port reception. 1 : = enable the serial port reception. tb8: = the 9th data bit, which will be transmitted in mode 2 and mode 3. rb8: = in mode 2 and 3, the received 9th data bit will be put into this bit. ti: = transmitting done flag. after a transmitting has been finished, the hardware will set this bit. ri: = receive done flag. after reception has been finished, the hardware will set this bit. sfr: sbuf (serial buffer) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 (data to be transmitted or received data) frame error detection when used for frame error detect, the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon .7 is determined by pcon.6 (smod0). if smod0 is set then scon.7 functions as fe . scon.7 functions as sm0 when smod0 is cleared. when used as fe, scon.7 can only be cleared by software. automatic address recognition there is an extra feature makes the devic e convenient to act as a master, which communicates to multiple slaves simultaneously. it is really automatic address recognition . there are two sfr saddr and saden implemented in the device. the user can read or write both of them. finally, the hardware will make use of these two sfr to ?generate? a ?compared byte?. the formula specifies as following. for example: set saddr = 11000000b set saden = 11111101b ? the achieved ?compared byte? will be ?110000x0? ( x means don?t care) for another example: set saddr = 11100000b set saden = 11111010b ? the achieved ?compared byte? will be ?11100x0x? after the generic ?compared byte? has been worked out, the stc11fxx will make use of this byte to determine how to set the bit ri in sfr scon . normally, an uart will set bit ri whenever it has done a byte reception; but for the uart in the stc11fxx, if the bit sm2 is set, it will set ri according to the following formula. www.datasheet.co.kr datasheet pdf - http://www..net/
32 stc11fxx technical summary in other words, not all data reception will respond to ri, while specific data does. by setting the saddr and the saden, the user can filter out those data byte that he doesn?t like to care. this feature brings great help to reduce software overhead. the above feature adapts to the serial port when operated in mode1, mode2, and mode3. dealing with mode 0, the user can ignore it. sfr : brt bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 it is used as the reload register for generating the baud-rate of the major uart sfr: auxr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t0x12 t1x12 urm0x6 brtr brtx12 s1brs t0x12 := set this bit to set the clock source for timer 0 is fosc, or clear it to set the clock source for timer 0 as fosc/12. t1x12 := set this bit to set the clock source for timer 0 is fosc, or clear it to set the clock source for timer 1 as fosc/12. urm0x6 := set this bit to set the clock source for the majo r uart is fosc/2, or clear it to set the clock source for or the major uart as fosc/12. brtr := setting this bit will enable the baud-rate generator of major uart to run. brtx12 := setting this bit can x12 the baud-rate of uart. s1brs := setting this bit can enable independence baud-rate generator www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 baud-rate generator and p1.05 programmable clock output st11fxx is able to generate a programmable clock output on p1.0. when brtclko bit in wake_clko is set, brt timer overflow pulse will toggle p1.0 latch to generate a 50% duty clock. the frequency of clock-out is as following : brtr fosc/12 8-bit timer overflow brt to major uart baud-rate generator for the secondary uart toggle p1.0 brtclko fosc 0 1 brtx12 clkout2 (1t mode) = 256 ? brt f osc/2 clkout2 (12t mode) = 256 ? brt f osc/24 www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 in system programming and in application programming in system programming (isp) to develop a good program for isp function, t he user has to understand the architecture of the embedded flash. the embedded flash consists of 128 pages. each page contains 512 bytes. dealing with flash, the user must erase it in page unit before writing (programming) data into it. erasing flash means setting the content of that flash as ff h. two erase modes are available in this chip. one is mass mode and the other is page mode . the mass mode gets more performance, but it erases the entire fl ash. the page mode is something performance less, but it is flexible since it erases flash in page unit. unlike ram?s real-time operation, to erase fl ash or to write (program) flash often takes long time so to wait finish. furthermore, it is a quite complex timing pr ocedure to erase/program flash. fortunately, the stc11fxx carried with convenient mechan ism to help the user read/change the flash content. just filling the target address and data into several sfr, and triggering the built-in isp automation, the user can easily er ase, read, and program the embedded flash. there are several sfr designed to help t he user implement the isp functionality. sfr: iap_data (iap flash data register) 0xc2h bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 data to be written into flash, or data got from flash iap_data is the data port register for is p/iap operation. the data in iap_data will be written into the desired address in operating isp/iap write and it is the data window of readout in operating isp read. sfr: iap_addrh (iap flash address high byte) 0xc3h bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 must be cleared to 000 isp/iap address high byte iap_addrh is the high byte address for all isp/iap operation. against in advertise effect, if one bit of iap_ addrh [7:5] is set, the isp write function must fail. sfr: iap_addrl (iap flash address low byte) 0xc4h bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 isp/iap address low byte iap_addrl is the low byte addres s for all isp/iap operation. www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 35 sfr: iap_cmd (isp flash-operating mode table) 0xc5h bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - - - - - mode selection mode selection to operate 0 0 standby 0 1 ap-memory read 1 0 ap-memory/data-flash program 1 1 ap-memory/data-flash page erase sfr: iap_trig (isp sequential command register to trigger isp/iap operation) 0xc6h bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 iap/sp-command iap_trig is the command port for triggering isp activity. if ia siap_trig is filled with sequential 5a h , a5 h and if iap_contr .7 = 1, isp activity will be triggered. when this register is read, the device id of stc11f xx will be returned (2 bytes). the msb byte of this device id is f2 h and lsb byte 02 h . isp_addrl .0 is used to select high/low byte of the device id. sfr: iap_contr (iap control register) 0xc7h bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 iapen swbs swrst cmd_fail - wait iapen: = determine if to enable isp/iap functionality 0 : = disable isp program to change flash. 1 : = enable isp program to change flash. swbs: = software boot entrance selector 0 : = boot from main-memory. 1 : = boot from isp memory. note: this bit will be loaded with hwbs(or0.3) after power-up moment. swrst: = software reset trigger setting this bit will ca use the device reset. cmd_fail: = isp/iap command fail flag 0 : = the last isp/iap command ha s finished successfully. 1 : = the last isp/iap command fails. it could be caused since the access of flash memory was inhibited. wait: = waiting time selection while the flash is busy. cpu wait time (oscillator cycle) iap_contr[2:0] page eras e program read recommended system clock 0 0 0 672384 1760 2 30m~24m 0 0 1 504288 1320 2 24m~20m 0 1 0 420240 1100 2 20m~12m 0 1 1 252144 660 2 12m~6m 1 0 0 126072 330 2 6m~3m 1 0 1 63036 165 2 3m~2m www.datasheet.co.kr datasheet pdf - http://www..net/
36 stc11fxx technical summary 1 1 0 42024 110 2 2m~1m 1 1 1 21012 55 2 < 1m procedures demonstrating isp function iapcmd xxxxx 011 b /* choice page-erasing command */ iap_contr 100xx010 b /* set ispen=1 to enable flash change. set wait=010, 10942 mc; assumed 10m x?s*/ iap_addrh (page address high byte) /* specify the address of the page to be erased */ iap_addrl (page address low byte) iap_trig 5ah /* trig iap activity */ iap_trig a5h (cpu progressing will be hold here ) (cpu continues) erase a specific flash page iapcmd xxxxx 010 b /* choice byte-programming command */ iap_contr 100xx010 b /* set ispen=1 to enable flash change. set wait=010, 60 mc; assumed 10m x?s*/ iap_addrh (address high byte) /* specify the address to be programmed */ iap_addrl (address low byte) iap_data (byte date to be written into flash) /* prepare data source */ iap_trig 5ah /* trig iap activity */ iap_trig a5h (cpu progressing will be hold here) (cpu continues) program a byte into flash iapcmd xxxxx 001 b /* choice byte-read command */ iap_contr 100xx010 b /* set iapen=1 to enable flash change. set wait=010, 11 mc; assumed 10m x?s*/ iap_addrh (address high byte) /* specify the address to be read */ iap_addrl (address low byte) scmd 5ah /* trig isp activity */ scmd a5h (cpu progressing will be hold here) (cpu continues and currently iap_data contain the desired data byte ) read a byte from flash www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 in-application program (iap) the in-application program feature is desi gned for user to read/write nonvolatile data flash . it may bring great help to store parameters those should be independent of power-up and power-done action. in other word s, the user can store data in data flash memory, and after he shutting down the mcu and rebooting the mcu, he can get the original value, which he had stored in. the user can program the data flash according to the same way as isp program, so he should get deeper understanding related to sfr iap_data, iap_addrl, iap_addrh, iap_cmd, iap_trig, and iap_contr . the data flash can be programmed by the ap program as well as the isp program. the isp program may program the ap memory and data flash , while the ap program may program the data flash but not the isp memory. if the ap program desires to change the isp memory associated with specific addre ss space, the hardware will ignore it. other auxiliary sfrs sfr: auxr1 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 uart_p1 - gf2- dps- uart_p1 := 0 : = disable 1 : = enable gf2 := general purpose flag. it can be used us a variable. dps := the switching bit for access of dual dptr. www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 built-in oscillator there is an oscillator built in the stc11fxx wh ich can be used as the oscillating source replacing the external crystal oscilla tor in some specific applications. to enable the built-in oscillator, an user must configure the device by clearing (enable) the bit via a general writer. making use of the built-in oscillator sa ves the cost of a crystal oscillator. typically, the frequency of the built-in oscillator is designed as 6mhz at 25 . dealing with temperature variation, the frequency could va ry from 4.2mhz to 7.8mhz (~30%). it is designed for applications which don?t ask very precise oscillating frequency, but not those applications asking high precision of oscillator frequency. www.datasheet.co.kr datasheet pdf - http://www..net/
stc technology co.,ltd. stc11f02 family STC11F01E/02e/04e/06 this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2008/12 version a1 instructions set data trasfer mnemonic description byt cyc mov a, rn move register to acc 1 1 mov a, direct move direct byte o acc 2 2 mov a, @ri move indirect ram to acc 1 2 mov a, #data move immediate data to acc 2 2 mov rn, a move acc to register 1 2 mov rn, direct move direct byte to register 2 4 mov rn, #data move immediate data to register 2 2 mov direct, a move acc to direct byte 2 3 mov direct, rn move register to direct byte 2 3 mov direct, direct move direct byte to direct byte 3 4 mov direct, @ri move indirect ram to direct byte 2 4 mov direct, #data move immediate data to direct byte 3 3 mov @ri, a move acc to indirect ram 1 3 mov @ri, direct move direct byte to indirect ram 2 3 mov @ri, #data move immediate data to indirect ram 2 3 mov dptr,#data16 load dptr with a 16-bit constant 3 3 movc a,@a+dptr move code byte relative to dptr to acc 1 4 movc a,@a+pc move code byte relative to pc to acc 1 4 movx a,@ri move on-chip auxiliary ram( 8-bit address) to acc 1 3 movx a,@dptr move on-chip auxiliary ram( 16-bit address) to acc 1 3 movx @ri,a move acc to on-chip auxiliary ram(8-bit address) 1 4 movx @dptr,a move acc to on-chip auxiliary ram(16-bit address) 1 3 movx a,@ri move external ram(8-bit address) to acc 1 7 movx a,@dptr move external ram(16-bit address) to acc 1 7 movx @ri,a move acc to external ram(8-bit address) 1 7 movx @dptr,a move acc to external ram(16-bit address) 1 7 push direct push direct byte onto stack 2 4 pop direct pop direct byte from stack 2 3 xch a, rn exchange register with acc 1 3 xch a, direct exchange direct byte with acc 2 4 xch a, @ri exchange indirect ram with acc 1 4 xchd a, @ri exchange low-order digit indirect ram with acc 1 4 arithematic operations mnemonic description byt cyc add a, rn add register to acc 1 2 add a, direct add direct byte to acc 2 3 add a, @ri add indirect ram to acc 1 3 add a, #data add immediate data to acc 2 2 addc a, rn add register to acc with carry 1 2 addc a, direct add direct byte to acc with carry 2 3 addc a, @ri add indirect ram to acc with carry 1 3 addc a, #data add immediate data to acc with carry 2 2 subb a, rn subtract register from acc with borrow 1 2 subb a, direct subtract direct byte from acc with borrow 2 3 subb a, @ri subtract indirect ram from acc with borrow 1 3 subb a, #data subtract immediate data from acc with borrow 2 2 inc a increment acc 1 2 inc rn increment register 1 3 inc direct increment direct byte 2 4 inc @ri increment indirect ram 1 4 dec a decrement acc 1 2 dec rn decrement register 1 3 www.datasheet.co.kr datasheet pdf - http://www..net/
40 stc11fxx technical summary dec direct decrement direct byte 2 4 dec @ri decrement indirect ram 1 4 inc dptr increment dptr 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 5 da a decimal adjust acc 1 4 logic operation mnemonic description byt cyc anl a, rn and register to acc 1 2 anl a, direct and direct byte to acc 2 3 anl a, @ri and indirect ram to acc 1 3 anl a, #data and immediate data to acc 2 2 anl direct, a and acc to direct byte 2 4 anl direct, #data and immediate data to direct byte 3 4 orl a, rn or register to acc 1 2 orl a, direct or direct byte to acc 2 3 orl a, @ri or indirect ram to acc 1 3 orl a, #data or immediate data to acc 2 2 orl direct, a or acc to direct byte 2 4 orl direct, #data or immediate data to direct byte 3 4 xrl a, rn exclusive-or register to acc 1 2 xrl a, direct exclusive-or direct byte to acc 2 3 xrl a, @ri exclusive-or indirect ram to acc 1 3 xrl a, #data exclusive-or immediate data to acc 2 2 xrl direct, a exclusive-or acc to direct byte 2 4 xrl direct, #data exclusive-or immediate data to direct byte 3 4 clr a clear acc 1 1 cpl a complement acc 1 2 rl a rotate acc left 1 1 rlc a rotate acc left through the carry 1 1 rr a rotate acc right 1 1 rrc a rotate acc right through the carry 1 1 swap a swap nibbles within the acc 1 1 boolean variable manipulation mnemonic description byt cyc clr c clear carry 1 1 clr bit clear direct bit 2 4 setb c set carry 1 1 setb bit set direct bit 2 4 cpl c complement carry 1 1 cpl bit complement direct bit 2 4 anl c, bit and direct bit to carry 2 3 anl c, /bit and complement of direct bit to carry 2 3 orl c, bit or direct bit to carry 2 3 orl c, /bit or complement of direct bit to carry 2 3 mov c, bit move direct bit to carry 2 3 mov bit, c move carry to direct bit 2 4 boolean variable branch mnemonic description byt cyc jc rel jump if carry is set 2 3 jnc rel jump if carry not set 2 3 jb bit, rel jump if direct bit is set 3 4 jnb bit, rel jump if direct bit not set 3 4 jbc bit, rel jump if direct bit is set and then clear bit 3 5 www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 41 proagram braching mnemonic description byt cyc acall addr11 absolute subroutine call 2 6 lcall addr16 long subroutine call 3 6 ret return from subroutine 1 4 reti return from interrupt subroutine 1 4 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if acc is zero 2 3 jnz rel jump if acc not zero 2 3 cjne a, direct, rel compare direct byte to acc and jump if not equal 3 5 cjne a, #data, rel compare immediate data to acc and jump if not equal 3 4 cjne rn, #data, rel compare immediate data to register and jump if not equal 3 4 cjne @ri, #data, rel compare immediate data to indirect ram and jump if not equal 3 5 djnz rn, rel decrement register and jump if not equal 2 4 djnz direct, rel decrement direct byte and jump if not equal 3 5 nop no operation 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/
42 stc11fxx technical summary absolute maximum rating (stc11fxx) *1 tested by sampling dc characteristics (stc11fxx) vss = 0v, ta = 25 , v cc = 5.0v unless otherwise specified symbol parameter test condition limits unit min typ max v ih1 input high voltage for p1 and p3 vcc=5.0v 2.0 v v ih2 input high voltage for reset pin vcc=5.0v 3.5 v v il input low voltage vcc=5.0v 0.8 v i ol output low current v pin =0.45v 12 20 ma i oh1 output high current(push-pull) v pin =2.4v 12 20 ma i oh2 output high current(quasi-bidirectional) v pin =2.4v 220 ua i il1 logic 0 input current(quasi-bidirectional) v pin =0.45v 17 50 ua i il2 logic 0 input curr ent(input-only) v pin =0.45v 0 10 ua i lk input leakage curr ent(open-drain output) v pin = v cc 0 10 ua i h2l logic 1 to 0 transition current v pin =1.8v 230 500 ua i op operating current f osc = 12mhz 12 30 ma i idle idle mode current f osc = 12mhz 6 15 ma i pd power down current v cc =5.0v 0.1 50 ua r rst internal reset pu ll-down resistance v cc =5.0v 100 kohm parameter rating operating voltage 4.5v ~ 5.5v operating temperature under bias -40 o c ~ 85 o c *1 storage temperature -40 o c ~ 125 o c voltage on any pin -0.5 ~ 5.5v operating frequency dc ~ 25mhz www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 43 absolute maximum rating (stc11lexx) parameter rating operating voltage 2.4v ~ 3.6v operating temperature under bias -40 o c ~ 85 o c *1 storage temperature -40 o c ~ 125 o c voltage on any pin -0.5 ~ 3.6v operating frequency dc ~ 25mhz *1 tested by sampling dc characteristics (stc11lexx) vss = 0v, ta = 25 , v cc = 3.3v unless otherwise specified symbol parameter test condition limits unit min typ max v ih1 input high voltage for p1 and p3 vcc=3.3v 2.0 v v ih2 input high voltage for reset pin vcc=3.3v 2.8 v v il input low voltage vcc=3.3v 0.8 v i ol output low current v pin =0.45v 8 14 ma i oh1 output high current(push-pull) v pin =2.4v 4 8 ma i oh2 output high current(quasi-bidirectional) v pin =2.4v 64 ua i il1 logic 0 input current(quasi-bidirectional) v pin =0.45v 7 50 ua i il2 logic 0 input curr ent(input-only) v pin =0.45v 0 10 ua i lk input leakage curr ent(open-drain output) v pin = v cc 0 10 ua i h2l logic 1 to 0 transition current(p1,3) v pin =1.4v 100 600 ua i op operating current f osc = 12mhz 9 15 ma i idle idle mode current f osc = 12mhz 3.5 6 ma i pd power down current v cc =3.3v 0.1 50 ua r rst internal reset pu ll-down resistance v cc =3.3v 100 kohm www.datasheet.co.kr datasheet pdf - http://www..net/
44 stc11fxx technical summary package dimension pdip-16 www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 45 pdip-18 www.datasheet.co.kr datasheet pdf - http://www..net/
46 stc11fxx technical summary pdip-18 sop-16 www.datasheet.co.kr datasheet pdf - http://www..net/
stc11fxx technical summary 47 sop-20 www.datasheet.co.kr datasheet pdf - http://www..net/
48 stc11fxx technical summary version history version date page description a1 2008/09 initial issue - - - www.datasheet.co.kr datasheet pdf - http://www..net/

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